Search results for "Arquitectura d'ordinadors"

showing 3 items of 3 documents

An Scalable matrix computing unit architecture for FPGA and SCUMO user design interface

2019

High dimensional matrix algebra is essential in numerous signal processing and machine learning algorithms. This work describes a scalable square matrix-computing unit designed on the basis of circulant matrices. It optimizes data flow for the computation of any sequence of matrix operations removing the need for data movement for intermediate results, together with the individual matrix operations’ performance in direct or transposed form (the transpose matrix operation only requires a data addressing modification). The allowed matrix operations are: matrix-by-matrix addition, subtraction, dot product and multiplication, matrix-by-vector multiplication, and matrix by scalar multiplication.…

Computer Networks and CommunicationsComputer scienceMathematicsofComputing_NUMERICALANALYSISSistemes informàticslcsh:TK7800-836002 engineering and technologyScalar multiplicationComputational scienceMatrix (mathematics)matrix-computing unitTranspose0202 electrical engineering electronic engineering information engineeringmatrix processorElectrical and Electronic EngineeringCirculant matrixcirculant matricesFPGA020208 electrical & electronic engineeringlcsh:ElectronicsDot productMatrix multiplicationArquitectura d'ordinadorsHardware and ArchitectureControl and Systems Engineeringmatrix arithmeticSignal Processing020201 artificial intelligence & image processingMultiplicationhardware implementation
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A Selective Change Driven System for High-Speed Motion Analysis.

2016

Vision-based sensing algorithms are computationally-demanding tasks due to the large amount of data acquired and processed. Visual sensors deliver much information, even if data are redundant, and do not give any additional information. A Selective Change Driven (SCD) sensing system is based on a sensor that delivers, ordered by the magnitude of its change, only those pixels that have changed most since the last read-out. This allows the information stream to be adjusted to the computation capabilities. Following this strategy, a new SCD processing architecture for high-speed motion analysis, based on processing pixels instead of full frames, has been developed and implemented into a Field …

Data streamMotion analysisLaser scanningComputer scienceReal-time computing02 engineering and technologylcsh:Chemical technology01 natural sciencesBiochemistryArticleAnalytical ChemistryInformàtica0202 electrical engineering electronic engineering information engineeringlcsh:TP1-1185data-flow architectureElectrical and Electronic EngineeringImage sensorhigh-speed visual acquisitionField-programmable gate arrayInstrumentationDataflow architecturePixellaser scanning020208 electrical & electronic engineering010401 analytical chemistryFrame (networking)Arquitectura d'ordinadorsAtomic and Molecular Physics and Optics0104 chemical sciencesCMOS image sensor; event-based vision; high-speed visual acquisition; data-flow architecture; FPGA system; laser scanningCMOS image sensorevent-based visionFPGA systemSensors (Basel, Switzerland)
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A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks

2019

New chips for machine learning applications appear, they are tuned for a specific topology, being efficient by using highly parallel designs at the cost of high power or large complex devices. However, the computational demands of deep neural networks require flexible and efficient hardware architectures able to fit different applications, neural network types, number of inputs, outputs, layers, and units in each layer, making the migration from software to hardware easy. This paper describes novel hardware implementing any feedforward neural network (FFNN): multilayer perceptron, autoencoder, and logistic regression. The architecture admits an arbitrary input and output number, units in la…

Hardware architectureFloating pointGeneral Computer ScienceArtificial neural networkComputer scienceClock rateActivation functionGeneral EngineeringSistemes informàticsAutoencoderArquitectura d'ordinadorsComputational scienceneural network accelerationFPGA implementationdeep neural networksMultilayer perceptronFeedforward neural networks - FFNNFeedforward neural networkXarxes neuronals (Informàtica)General Materials Sciencelcsh:Electrical engineering. Electronics. Nuclear engineeringlcsh:TK1-9971systolic hardware architectureIEEE Access
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